Introduction 1
Prepation 2-6
Application 6-12
Acnowledgement 12-14
References 14
Introduction:-
1950s, Stanford Ovshinsky created an entirely new realm of materials science, which in turn has given new life to the engineering of semiconductors, solar energy, and electric cars.
Stan Ovshinsky was born in Akron, Ohio in 1922. After graduating from high school, he went straight to work. In 1955, he began working the field of amorphous materials, that is, materials that lack a definite crystalline structure. Ovshinsky was the first engineer to devise a method, called "phase change," for crystalizing these disordered materials, with resulting novel uses: for example, films that gain metallic properties without losing their original optical capabilities. One result was amorphous semiconductors --- which the engineering community had previously considered an utter impossibility.
In 1960, Ovshinsky founded Energy Conversion Devices, Inc. (ECD), in order to continue and expand his work in amorphous semiconductors. Meanwhile, engineers nationwide had eagerly entered an entirely new field: "ovonics" (from Ovshinsky Electronics).
Ovshinsky earned numerous patents in the 1970s and '80s for amorphous semiconductor materials. These materials became essential to optoelectronic copying and fax machines, as well as large, flat-panel liquid crystal displays like those of computer monitors. As early as 1970, Ovshinsky had used his ovonic phase change principle to invent a reversible optical memory disk: that is, a prototype rewritable CD-ROM. Today, thirteen high tech companies around the world are developing rewritable CDs using Ovshinsky's technology.
Ovshinsky went on to use his thin-film amorphous silicon to invent a manufacturing method that might do for solar energy what the assembly line did for automobiles. In 1983, he patented a system that allowed photovoltaic solar panels to be manufactured in continuous rolls 1000 feet in length. Ovshinsky's "Continuous Amorphous Solar Cell Production System" operates much like a newspaper rollpress, speedily imprinting a plasma of amorphous silicon semiconductors in a continuous web onto a thin, anodized metal sheet.
The high energy-conversion efficiency of the thin-film cells and the high throughput of the process make Ovshinsky's photovoltaic cells a revolutionary leap forward for solar energy. They have been installed at various sites around and above the globe, from Mexican mountain villages to the Mir space station. Ovshinsky's "Uni-Solar" roofing tiles, for residential buildings, have won Popular Science's "Best of What's New" Grand Award (1996) and Discover Magazine's Discover Award in the Environment category (1997).
PREPARATION:-
1. Process for the preparation of thin semiconductor material films, wherein the process comprises subjecting a semiconductor material wafer having a planar face and whose planeid="DEL-S-00001" date="20070206" ,id="DEL-S-00001" is substantially parallel to a principal crystallographic plane, to the three following stages:
a first stage of implantation by ion bombardment of the face of said wafer by means of ions creating in the volume of said wafer at a depth close to the average penetration depth of said ions, a layer of gaseous microbubbles defining in the volume of said wafer a lower region constituting a majority of the substrate and an upper region constituting the thin id="INS-S-00001" date="20070206" semiconductor material id="INS-S-00001" film, the ions being id="DEL-S-00002" date="20070206" chosen from amongid="DEL-S-00002" hydrogen gas ions id="DEL-S-00003" date="20070206" or rare gas ionsid="DEL-S-00003" andid="INS-S-00002" date="20070206" , wherein id="INS-S-00002" the temperature of the wafer during implantation id="DEL-S-00004" date="20070206" beingid="DEL-S-00004" id="INS-S-00003" date="20070206" is id="INS-S-00003" kept below the temperature at which the gas produced by the implanted ions can escape from the semiconductor by diffusion,
a second stage of intimately contacting the planar face of said wafer with a stiffener constituted by at least one rigid material layer,
a third stage of thermally treating the assembly of said wafer and said stiffener at a temperature above that at which the ion bombardment takes place and adequate to create by a crystalline rearrangement effect in the waferid="INS-S-00004" date="20070206" , a coalescence of hydrogen microbubbles id="INS-S-00004" and a pressure effect in the id="INS-S-00005" date="20070206" hydrogen id="INS-S-00005" microbubbles, a separation between the thin id="INS-S-00006" date="20070206" semiconductor material id="INS-S-00006" film and the majority of the substrate, the stiffener and the planar face of the wafer being kept in intimate contact during said stage.
2. Process for the preparation of thin id="INS-S-00007" date="20070206" semiconductor material id="INS-S-00007" films according to claim 1, wherein the stage of implanting ions in the semiconductor material takes place through one or more layers of materials having a nature and thickness such that they can be traversed by the ions.
3. Process for the id="DEL-S-00005" date="20070206" productionid="DEL-S-00005" id="INS-S-00008" date="20070206" preparation id="INS-S-00008" of thin id="INS-S-00009" date="20070206" semiconductor material id="INS-S-00009" films according to claim 1, wherein the semiconductor comprises a group IV material.
4. Process for the id="DEL-S-00006" date="20070206" productionid="DEL-S-00006" id="INS-S-00010" date="20070206" preparation id="INS-S-00010" of thin id="INS-S-00011" date="20070206" semiconductor material id="INS-S-00011" films id="DEL-S-00007" date="20070206" according to claim 1id="DEL-S-00007" , wherein the id="INS-S-00012" date="20070206" process comprises subjecting a id="INS-S-00012" semiconductor id="DEL-S-00008" date="20070206" isid="DEL-S-00008" id="INS-S-00013" date="20070206" material wafer of id="INS-S-00013" siliconid="DEL-S-00009" date="20070206" ,id="DEL-S-00009" id="INS-S-00014" date="20070206" having a planar face and whose plane is substantially parallel to a principal crystallographic plane, to the three following stages:
a first stage of implantation by ion bombardment of the face of said wafer by means of ions creating in the volume of said wafer at a depth close to the average penetration depth of said ions, a layer of gaseous microbubbles defining in the volume of said wafer a lower region constituting a majority of the substrate and an upper region constituting the thin semiconductor material film, wherein id="INS-S-00014" the implanted id="DEL-S-00010" date="20070206" ion is aid="DEL-S-00010" id="INS-S-00015" date="20070206" ions are id="INS-S-00015" hydrogen gas id="DEL-S-00011" date="20070206" ion,id="DEL-S-00011" id="INS-S-00016" date="20070206" ions and id="INS-S-00016" the wafer temperature during implantation is id="INS-S-00017" date="20070206" kept below the temperature at which the gas produced by the implanted ions can escape from the semiconductor by diffusion and id="INS-S-00017" between 20° and 450° C.id="INS-S-00018" date="20070206" , id="INS-S-00018" id="DEL-S-00012" date="20070206" andid="DEL-S-00012"
id="INS-S-00019" date="20070206" a second stage of intimately contacting the planar face of said wafer with a stiffener constituted by at least one rigid material layer, and
a third stage of thermally treating the assembly of said wafer and said stiffener at a temperature above that at which the ion bombardment takes place and adequate to create by a crystalline rearrangement effect in the wafer and a pressure effect in the microbubbles, a separation between the thin semiconductor material film and the majority of the substrate, the stiffener and the planar face of the wafer being kept in intimate contact during said stage,
wherein id="INS-S-00019" the temperature of the third heat treatment stage exceeds 500° C.
5. Process for the id="DEL-S-00013" date="20070206" productionid="DEL-S-00013" id="INS-S-00020" date="20070206" preparation id="INS-S-00020" of thin id="INS-S-00021" date="20070206" semiconductor material id="INS-S-00021" films according to claim 2, wherein implantation takes place through an encapsulating thermal silicon oxide layer and the stiffener is a silicon wafer covered by at least one silicon oxide layer.
6. Process for the id="DEL-S-00014" date="20070206" productionid="DEL-S-00014" id="INS-S-00022" date="20070206" preparation id="INS-S-00022" of thin id="INS-S-00023" date="20070206" semiconductor material id="INS-S-00023" films according to claim 1, wherein the second stage of intimately contacting the planar face of said wafer with a stiffener takes place by applying an electrostatic pressure.
7. Process for the id="DEL-S-00015" date="20070206" productionid="DEL-S-00015" id="INS-S-00024" date="20070206" preparation id="INS-S-00024" of thin id="INS-S-00025" date="20070206" semiconductor material id="INS-S-00025" films according to claim 1, wherein the stiffener is deposited by one or more methods from within the group consisting of evaporation, sputtering, and chemical vapor deposition with or without plasma assistance or photon assistance.
8. Process for the id="DEL-S-00016" date="20070206" productionid="DEL-S-00016" id="INS-S-00026" date="20070206" preparation id="INS-S-00026" of thin id="INS-S-00027" date="20070206" semiconductor material id="INS-S-00027" films according to claim 1, wherein the stiffener is bonded to said wafer by means of an adhesive substrate.
9. Process for the id="DEL-S-00017" date="20070206" productionid="DEL-S-00017" id="INS-S-00028" date="20070206" preparation id="INS-S-00028" of thin id="INS-S-00029" date="20070206" semiconductor material id="INS-S-00029" films according to claim 1, wherein the stiffener is made to adhere to the wafer by a treatment favoring interatomic bonds.
id="INS-S-00030" date="20070206" 10. Process for the preparation of thin semiconductor material films according to claim 1 further comprising cleaving the thin semiconductor material film from the substrate. id="INS-S-00030"
id="INS-S-00031" date="20070206" 11. Process for the preparation of thin semiconductor material films according to claim 1, wherein the thin semiconductor material films are formed as a continuous film of semiconductor material. id="INS-S-00031"
id="INS-S-00032" date="20070206" 12. Process for the preparation of thin semiconductor material films according to claim 1, wherein the semiconductor material wafer comprises silicon. id="INS-S-00032"
id="INS-S-00033" date="20070206" 13. Process for the preparation of thin semiconductor material films according to claim 1, wherein the semiconductor material wafer comprises germanium. id="INS-S-00033"
id="INS-S-00034" date="20070206" 14. Process for the preparation of thin semiconductor material films according to claim 1, wherein the semiconductor material wafer comprises a silicon-germanium alloy. id="INS-S-00034"
id="INS-S-00035" date="20070206" 15. Process for the preparation of thin semiconductor material films according to claim 1, wherein the semiconductor material wafer comprises silicon carbide. id="INS-S-00035"
id="INS-S-00036" date="20070206" 16. Process for the preparation of thin semiconductor material films according to claim 1, wherein the stiffener comprises a silicon wafer covered by at least one silicon oxide layer. id="INS-S-00036"
id="INS-S-00037" date="20070206" 17. Process for the preparation of thin semiconductor material films, wherein the process comprises subjecting a semiconductor material wafer having a planar face and whose plane is substantially parallel to a principal crystallographic plane, to the three following stages:
a first stage of implantation by hydrogen ion bombardment of the face of said wafer by means of hydrogen ions creating in the volume of said wafer at a depth close to the average penetration depth of said ions, a layer of gaseous microbubbles defining in the volume of said wafer a lower region constituting a majority of the substrate and an upper region constituting the thin semiconductor material film, wherein the temperature of the wafer during implantation is kept below the temperature at which the gas produced by the implanted ions can escape from the semiconductor by diffusion,
a second stage of intimately contacting the planar face of said wafer with a stiffener constituted by at least one rigid material layer,
a third stage of thermally treating the assembly of said wafer and said stiffener at a temperature above that at which the ion bombardment takes place and adequate to create by a crystalline rearrangement effect in the wafer, a coalescence of hydrogen microbubbles and a pressure effect in the hydrogen microbubbles, a separation between the thin semiconductor material film and the majority of the substrate, the stiffener and the planar face of the wafer being kept in intimate contact during said stage. id="INS-S-00037"
id="INS-S-00038" date="20070206" 18. Process for the preparation of thin semiconductor material films according to claim 17, wherein the stage of implanting ions in the semiconductor material takes place through one or more layers of materials having a nature and thickness such that they can be traversed by the ions. id="INS-S-00038"
id="INS-S-00039" date="20070206" 19. Process for the preparation of thin semiconductor material films according to claim 17, wherein the semiconductor material comprises a group IV semiconductor. id="INS-S-00039"
id="INS-S-00040" date="20070206" 20. Process for the preparation of thin semiconductor material films according to claim 17, wherein the semiconductor material wafer comprises silicon.id="INS-S-00040"
id="INS-S-00041" date="20070206" 21. Process for the preparation of thin semiconductor material films according to claim 17, wherein the semiconductor material wafer comprises germanium. id="INS-S-00041"
id="INS-S-00042" date="20070206" 22. Process for the preparation of thin semiconductor material films according to claim 17, wherein the semiconductor material wafer comprises a silicon-germanium alloy. id="INS-S-00042"
id="INS-S-00043" date="20070206" 23. Process for the preparation of thin semiconductor material films according to claim 17, wherein the semiconductor material wafer comprises silicon carbide. id="INS-S-00043"
id="INS-S-00044" date="20070206" 24. Process for the preparation of thin semiconductor material films according to claim 17, wherein implantation takes place through an encapsulating thermal silicon oxide layer. id="INS-S-00044"
id="INS-S-00045" date="20070206" 25. Process for the preparation of thin semiconductor material films according to claim 17, wherein the stiffener comprises a silicon wafer covered by at least one silicon oxide layer. id="INS-S-00045"
id="INS-S-00046" date="20070206" 26. Process for the preparation of thin semiconductor material films according to claim 17, wherein the second stage of intimately contacting the planar face of said wafer with a stiffener takes place by applying an electrostatic pressure. id="INS-S-00046"
id="INS-S-00047" date="20070206" 27. Process for the preparation of thin semiconductor material films according to claim 17, wherein the stiffener is deposited by one or more methods from within the group consisting of evaporation, sputtering, and chemical vapor deposition with or without plasma assistance or photon assistance. id="INS-S-00047"
id="INS-S-00048" date="20070206" 28. Process for the preparation of thin semiconductor material films according to claim 17, wherein the stiffener is bonded to said wafer by means of an adhesive substance. id="INS-S-00048"
id="INS-S-00049" date="20070206" 29. Process for the preparation of thin semiconductor material films according to claim 17, wherein the stiffener is made to adhere to the wafer by a treatment favoring interatomic bonds. id="INS-S-00049"
id="INS-S-00050" date="20070206" 30. Process for the preparation of thin semiconductor material films according to claim 17, which further comprises cleaving the thin semiconductor material film from the substrate. id="INS-S-00050"
id="INS-S-00051" date="20070206" 31. Process for the preparation of thin films according to claim 17, wherein the thin semiconductor material films are formed as a continuous film of semiconductor material. id="INS-S-00051"
id="INS-S-00052" date="20070206" 32. Process for the preparation of thin semiconductor material films, wherein the process comprises subjecting a semiconductor material wafer having a planar face and whose plane is substantially parallel to a principal crystallographic plane, to the three following stages:
a first stage of implantation by ion bombardment of the face of said wafer by means of ions creating in the volume of said wafer at a depth close to the average penetration depth of said ions, a layer of gaseous microbubbles defining in the volume of said wafer a lower region constituting a majority of the substrate and an upper region constituting the thin semiconductor material film, the ions consisting of hydrogen gas ions and, wherein the temperature of the wafer during implantation is kept below the temperature at which the gas produced by the implanted ions can escape from the semiconductor by diffusion,
a second stage of intimately contacting the planar face of said wafer with a stiffener constituted by at least one rigid material layer,
a third stage of thermally treating the assembly of said wafer and said stiffener at a temperature above that at which the ion bombardment takes place and adequate to create by a crystalline rearrangement effect in the wafer, a coalescence of hydrogen microbubbles and a pressure effect in the hydrogen microbubbles, a separation between the thin semiconductor material film and the majority of the substrate, the stiffener and the planar face of the wafer being kept in intimate contact during said stage. id="INS-S-00052"
id="INS-S-00053" date="20070206" 33. Process for the preparation of thin semiconductor material films according to claim 32, wherein the stage of implanting ions in the semiconductor material takes place through one or more layers of materials having a nature and thickness such that they can be traversed by the ions. id="INS-S-00053"
id="INS-S-00054" date="20070206" 34. Process for the preparation of thin semiconductor material films according to claim 32, wherein the semiconductor material comprises a group IV semiconductor. id="INS-S-00054"
id="INS-S-00055" date="20070206" 35. Process for the preparation of thin semiconductor material films according to claim 32, wherein the semiconductor material wafer comrises silicon. id="INS-S-00055"
id="INS-S-00056" date="20070206" 36. Process for the preparation of thin semiconductor material films according to claim 32, wherein the semiconductor material wafer comrises germanium. id="INS-S-00056"
id="INS-S-00057" date="20070206" 37. Process for the preparation of thin semiconductor material films according to claim 32, wherein the semiconductor material wafer comrises a silicon-germanium alloy. id="INS-S-00057"
id="INS-S-00058" date="20070206" 38. Process for the preparation of thin semiconductor material films according to claim 32, wherein the semiconductor material wafer comrises silicon carbide. id="INS-S-00058"
id="INS-S-00067" date="20070206" 47. Process for the preparation of thin semiconductor material films, wherein the process comprises subjecting a semiconductor material wafer having a planar face and whose plane is substantially parallel to a principal crystallographic plane, to the three following stages:
a first stage of implantation by hydrogen ion bombardment of the face of said wafer so as to create in the volume of said wafer at a depth close to the average penetration depth of said ions, a layer of gaseous hydrogen microbubbles defining in the volume of said wafer a lower region constituting a majority of the substrate and an upper region constituting the thin semiconductor material film, wherein the temperature of the wafer during implantation is kept below the temperature at which the gas produced by the implanted ions can escape from the semiconductor by diffusion;
a second stage of intimately contacting the planar face of said wafer with a stiffener constituted by at least one rigid material layer, and
a third stage of thermally treating the assembly of said wafer and said stiffener at a temperature above that at which the ion bombardment takes place and adequate to create by a crystalline rearrangement effect in the wafer and a pressure effect in the microbubbles, a separation between the thin semiconductor material film and the majority of the substrate, the stiffener and the planar face of the wafer being kept in intimate contact during said stage. id="INS-S-00067"
id="INS-S-00068" date="20070206" 48. Process for the preparation of thin semiconductor material films according to claim 47, wherein the stage of implanting ions in the semiconductor material takes place through one or more layers of materials having a nature and thickness such that they can be traversed by the ions. id="INS-S-00068"
id="INS-S-00069" date="20070206" 49. Process for the preparation of thin semiconductor material films according to claim 47, wherein the semiconductor material comprises a group IV semiconductor. id="INS-S-00069"
id="INS-S-00070" date="20070206" 50. Process for the preparation of thin semiconductor material films according to claim 47, wherein the semiconductor material wafer comprises silicon. id="INS-S-00070"
id="INS-S-00071" date="20070206" 51. Process for the preparation of thin semiconductor material films according to claim 47, wherein the semiconductor material wafer comprises germanium. id="INS-S-00071"
id="INS-S-00072" date="20070206" 52. Process for the preparation of thin semiconductor material films according to claim 47, wherein the semiconductor material wafer comprises a silicon-germanium alloy. id="INS-S-00072"
id="INS-S-00073" date="20070206" 53. Process for the preparation of thin semiconductor material films according to claim 47, wherein the semiconductor material wafer comprises silicon carbide. id="INS-S-00073"
id="INS-S-00074" date="20070206" 54. Process for the preparation of thin semiconductor material films according to claim 47, wherein implantation takes place through an encapsulating thermal silicon oxide layer. id="INS-S-00074"
id="INS-S-00075" date="20070206" 55. Process for the preparation of thin semiconductor material films according to claim 47, wherein the stiffener comprises a silicon wafer covered by at least one silicon oxide layer. id="INS-S-00075"
id="INS-S-00076" date="20070206" 56. Process for the preparation of thin semiconductor material films according to claim 47, wherein the second stage of intimately contacting the planar face of said wafer with a stiffener takes place by applying an electrostatic pressure. id="INS-S-00076"
id="INS-S-00077" date="20070206" 57. Process for the preparation of thin semiconductor material films according to claim 47, wherein the stiffener is deposited by one or more methods from within the group consisting of evaporation, sputtering, and chemical vapor deposition with or without plasma assistance or photon assistance. id="INS-S-00077"
id="INS-S-00078" date="20070206" 58. Process for the preparation of thin semiconductor material films according to claim 47, wherein the stiffener is bonded to said wafer by means of an adhesive substance. id="INS-S-00078"
id="INS-S-00079" date="20070206" 59. Process for the preparation of thin semiconductor material films according to claim 47, wherein the stiffener is made to adhere to the wafer by a treatment favoring interatomic bonds. id="INS-S-00079"
id="INS-S-00080" date="20070206" 60. Process for the preparation of thin semiconductor material films according to claim 47, which further comprises cleaving the thin semiconductor material film from the substrate. id="INS-S-00080"
id="INS-S-00081" date="20070206" 61. Process for the preparation of thin films according to claim 47, wherein the thin semiconductor material film is formed as a continuous film of semiconductor material. id="INS-S-00081"
id="INS-S-00082" date="20070206" 62. Process for the preparation of thin semiconductor material films, wherein the process comprises subjecting a semiconductor material wafer having a planar face and whose plane is substantially parallel to a principal crystallographic plane, to the three following stages:
a first stage of implantation by ion bombardment of the face of said wafer by means of hydrogen ions creating, by electronic braking in the wafer, in the volume of said wafer at a depth close to the average penetration depth of said ions, a layer of gaseous hydrogen microbubbles defining in the volume of said wafer a lower region constituting a majority of the substrate and an upper region constituting the thin semiconductor material film, wherein the temperature of the wafer during implantation is kept below the temperature at which the gas produced by the implanted ions can escape from the semiconductor by diffusion;
a second stage of intimately contacting the planar face of said wafer with a stiffener constituted by at least one rigid material layer,
a third stage of thermally treating the assembly of said wafer and said stiffener at a temperature above that at which the ion bombardment takes place and adequate to create by a crystalline rearrangement effect in the wafer and a coalescence of hydrogen microbubbles and a pressure effect in the hydrogen microbubbles, a separation between the thin semiconductor material film and the majority of the substrate, the stiffener and the planar face of the wafer being kept in intimate contact during said stage. id="INS-S-00082"
This thesis deals with the preparation methodologies and the microstructural characteristics concerning semiconductor thin films (including SnO2 thin films, Au/Ge bilayer films, and Pd-Ge alloy thin films) and the metal oxides (including SnO, SnO2, Mn2O3 and Mn3O4 nanocrystals: nanoparticles, nanowires, nanorods, and nanofractals). Firstly, the preparation methodologies and the microstructural characteristics of tin oxides have been investigated in detail and described in chapter 2. This covers the following: (i) the application of x-ray diffraction, scanning electron microscopy, transmission electron microscopy, and high resolution transmission electron microscopy to study tin oxide thin films deposited on Si (100) substrates at room temperature using pulsed laser deposition (PLD) techniques with a sintered cassiterite and subsequently heat-treated tin oxide thin films; (ii) measurement of surface topographies of SnO2 thin films prepared by PLD for various substrate temperatures by scanning electron microscopy, where the concept of fractal geometry was proven useful in describing structures and processes in experimental systems; (iii) preparation of low-dimensional nanostructures of SnO2 thin films with some interesting features of tetragonal rutile structure by PLD, where the as-prepared SnO2 thin films were found to be in the polycrystalline state; (iv) growth of nanocrystalline SnO2 thin films onto glass substrates by PLD, where the thin films were determined to be a polycrystalline SnO2 and an amorphous SnO phase. The nucleation and growth processes of SnO2 nanocrystallites were analysed in detail in order to examine how the PLD technique and operating conditions affect the evolution of grain size, shape, crystallographic characteristics and morphology; (v) experimental and theoretical exploration of quantum dot formation and dynamic scaling behavior of SnO2 nanocrystals in coalescence regime for growth by PLD; (vi) investigation of the mystery of porous SnO2 thin film formation by pulsed delivery based on sintered SnO2 target at room temperature; (vii) preparation of a pure orthorhombic SnO2 thin film by PLD at much lower pressures and temperatures than those of traditional methods; (viii) demonstration that SnO2 nanowires can be synthesized by a PLD process deposited on Si (100) substrates at room temperature; and (ix) synthesis of SnO2 nanorods in bulk quantity by a calcining process based on annealing precursor powders. Secondly, the extended version of metal/semiconductor thin films for the crystallization of amorphous Ge, and the formation of nanocrystals and compounds developed with improved micro- and nanostructured features are described in chapter 3. This chapter includes: (i) investigation of microstructural changes and fractal Ge nanocrystallites in polycrystalline Au/amorphous Ge bilayer films upon annealing by scanning electron microscopy, transmission electron microscopy and x-ray energy-dispersive spectroscopy; (ii) interdiffusion assessment of nanoparticles in fat fractal patterns, where the nanoparticles of polycrystalline Ge have been grown in a freshly cleaved single crystal NaCl (100) substrate, starting from Au/Ge bilayer films prepared by evaporation method during annealing; (iii) investigation of nanocrystal formation and fractal microstructural assessment in Au/Ge bilayer films upon annealing by high-resolution transmission electron microscopy, where the crystallization process was suggested to be a diffusion controlled and random successive nucleation and growth mechanism; (iv) investigation of solid-state reactions and amorphous Ge crystallization for various ratios of thickness (or composition) in Pd-Ge alloy thin films after annealing by transmission electron microscopy; and (v) analysis of grain nucleation, growth and aggregation in Pd-Ge alloy thin films during annealing by fundamental kinetic processes. Thirdly, a novel selective synthesis route for various morphologies of manganese oxides nanocrystals (including nanoparticles, nanorods and nanofractals) and their unique microstructural characteristics are presented in chapter 4. Intricate fundamental properties of manganese oxides nanocrystals are studied. This includes: (i) investigation of the influence of grain size on the vibrational properties of Mn2O3 nanocrystals by Raman and Infrared spectroscopy; (ii) investigation of isothermal grain growth of Mn2O3 nanocrystals at various temperatures between 200 and 500 °C for different annealing times and analyzing the grain growth data using two different models; and (iii) development of a widely applicable chemical reaction route to prepare single-crystal Mn3O4 nanocrystals including nanoparticles, nanorods and nanofractals. The Mn3O4 nanocrystals with tetragonal structure were prepared synchronously by a chemical liquid homogeneous precipitation method, which has been employed to synthesize these nanostructured materials using reactants of MnCl2•4H2O, H2O2, and NaOH under the environment of a suitable surfactant and alkaline solution. To sum up, it is expected that the fabrication methodologies developed and the knowledge of microstructural evolution gained in semiconductor thin films (including SnO2 thin films, Au/Ge bilayer films, and Pd-Ge alloy thin films) and metal oxides (including SnO, SnO2, Mn2O3 and Mn3O4 nanocrystals: nanoparticles, nanowires, nanorods, and nanofractals) will provide an important fundamental basis underpinning further interdisciplinary (physics, chemistry and materials science) research in this field leading to promising exciting opportunities for future technological applications involving these thin film materials.
Semiconductor thin films and their application to dye-sensitized solar cells
Cathodic electrodeposition of titanium dioxide (TiO2) and zinc oxide (ZnO) thin films has been studied in the aim of developing cost-effective alternative routes to the photoelectrode materials for dye-sensitized solar cells (DSCs). Preparation of porous anatase TiO2 thin film modified by cis-dithiocyanato bis(4,4′-dicarboxylic acid-2,2′-bipyridine)ruthenium(II) (N3) dye has been achieved by a three-step process: cathodic electrodeposition of a Ti hydroxide thin film from an acidic aqueous solution containing TiOSO4, H2O2 and KNO3, heat treatment of the film at 400 °C and chemical adsorption of dyes from solution. The photocurrent action spectrum measured at the N3-modified TiO2 thin film electrode in contact with I−/I3− redox electrolyte solution revealed incident photon to current conversion efficiency (IPCE) of 37% in the visible range. While TiO2 needed heat treatment for crystallization, direct electrodeposition of crystalline ZnO was possible from an aqueous solution of Zn(NO3)2. Addition of N3 to the deposition bath made it possible to synthesize porous ZnO/N3 hybrid thin film in one step. IPCE of 24% has been achieved for this film. A sandwich cell using the electrodeposited ZnO/N3 hybrid thin film photoelectrode measured Isc=0.61 mA/cm2, Voc=0.46 V, F.F.=0.46 and η=0.13% under illumination by an artificial light source (500-W Xe lamp equipped with a <420-nm and an IR cutoff filters, INTENSITY=100 mW cm−2), being the first example of a real working DSC fabricated without any heat treatment
ACKNOWLEDGMENTS
We are grateful to Professor Normand Mousseau for sending
us his models of amorphous silicon. We also acknowledge
the support of the National Science Foundation under
Grant Nos. DMR-0074624, DMR-0310933, and DMR-
0205858. P.O. acknowledges support for his research visit to
Ohio University from the Programa de Movilidad de Investigadores
of Ministerio de Educacio´n y Cultura of Spain.
*Electronic address: drabold@helios.phy.ohiou.edu
1 See, for instance, S.R. Elliot, Physics of Amorphous Materials
~Longman, London, 1984!.
2R. Biswas, C.Z. Wang, C.T. Chan, K.M. Ho, and C.M. Soukoulis,
Phys. Rev. Lett. 63, 1491 ~1989!.
3D.C. Allan and E.J. Melle, Phys. Rev. B 31, 5565 ~1985!.
4P.A. Fedders and A.E. Carlsson, Phys. Rev. B 39, 1134 ~1989!.
5 J. Holender and G. Morgan, J. Phys.: Condens. Matter 4, 4473
~1992!.
6 S. Kneif and W. von Neissen, Phys. Rev. B 58, 4459 ~1998!.
7 B.J. Min, Y.H. Lee, C.Z. Wang, C.T. Chan, and K.M. Ho, Phys.
Rev. B 45, 6839 ~1992!.
8W. Kohn and L.J. Sham, Phys. Rev. 140, A1133 ~1965!.
9P.A. Fedders and D.A. Drabold, Phys. Rev. B 47, 13 277 ~1993!.
10D.K. Biegelsen and M. Stutzmann, Phys. Rev. B 33, 3006 ~1986!.
11T. Umeda, S. Yamasaki, J. Isoya, and K. Tanaka, Phys. Rev. B 59,
4849 ~1999!.
12P.A. Fedders, D.A. Drabold, P. Ordejon, G. Fabricius, D.
Sanchez-Portal, E. Artcho, and J.M. Soler, Phys. Rev. B 60,
10 594 ~1999!.
13P. Hohenberg and W. Kohn, Phys. Rev. 136, B864 ~1965!.
14M.S. Hybertsen and S.G. Louie, Phys. Rev. B 34, 5390 ~1986!.
15B.G. Pfrommer and S.G. Louie, Phys. Rev. B 58, 12 680 ~1998!.
16 J.-L. Li, G.-M. Rignanese, E.K. Chang, X. Blase, and S.G. Louie,
Phys. Rev. B 66, 035102 ~2002!.
17G.T. Barkema and N. Mousseau, Phys. Rev. B 62, 4985 ~2000!.
References :-
-http://lib.cityu.edu.hk/record=b2217892
-www.google .com
-www.answer.com
No comments:
Post a Comment